Programming of Flashes, FPGAs, PLDs, Microcontrollers and others
The boundary scan controller can also be used to program devices via the JTAG interface. The programming speed depends on the performance of the boundary scan controller and of course on the size of the programming file. To save programming time, several boards can be programmed in parallel (GANG programming). The TCK Frequency that can be reached is also decisive for the programming time. Good termination on the test bus signals is crucial here. A buffer for the test bus signals is advantageous in many cases.
All types of parallel or serial flashes can be programmed. In this example, these are a parallel (NAND or NOR Flash), a serial Flash (EEPROM) and the boot flash for the FPGA.
It is also possible to program PLDs and to configure FPGAs.
Used file formats are Serial Vector Files (SVF) or JAM Standard Test and Programming Language files (JAM, STAPL). Also the Standard IEEE1532 for In-system Configuration of Programmable Devices is supported.
The programming time for large flash memories and especially for large boot flashes is usually very long.
This time can be shortened considerably by using ChipVORX® technology. ChipVORX® is a technology that was developed by Testonica Lab together with GOEPEL electronics and that GOEPEL Electronics seamlessly integrates into SYSTEM CASCON..
In practice, the ChipVORX® IPs achieve drastic accelerations for larger FPGA types compared to standard Boundary Scan programming methods.
While typical values for parallel flashes are in the range of 10x to 15x, the factor for serial flashes, where the configuration time becomes very critical, can easily go up to 100x.
It îs not possible to program On-Chip Flashes of microcontrollers via Boundary Scan.
But with the VarioTAP IP technology GOEPEL Electronics integrates seamlessly a processor emulation technology into SYSTEM CASCON. The processor is used by a processor-specific model for both on-chip Flash programming and external Flash programming .